1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. More particularly, the present invention relates to a semiconductor device having a Metal-Oxide Semiconductor (MOS) field-effect transistor. The invention also pertains to a method for manufacturing the semiconductor device.
2. Description of the Related Art
For one technique for speeding up an operating speed of a MOS field-effect transistor (hereinafter, referred to as a MOSFET), a “strain technique” for applying a predetermined stress to a channel and imparting a strain to a channel crystal to thereby improve a channel mobility of carriers is being taken notice of.
Examples of the technique for applying a stress to a channel portion include a technique for changing a material filled within a Shallow Trench Isolation (STI) as an element isolation region to change a stress applied to a channel, a technique for embedding a material having a lattice constant different from that of a silicon substrate into a source region or a drain region to apply a stress to a channel, and a technique for forming a silicide on a source region or a drain region to apply a stress to a channel by a thermal expansion difference between the silicide and a silicon substrate.
In addition, examples thereof include a technique for covering the MOSFET with a Contact Etching Stop Liner film (hereinafter, referred to as a CESL film) to apply a stress to a channel using a intrinsic stress of the CESL film. According to this technique, a stress can be inexpensively applied to a channel.
For an example using such a stress film, for example, Japanese Unexamined Patent Publication No. 2005-5633 discloses a semiconductor device in which a stress film is formed on a source region and a drain region to apply a stress to a channel.
In the case of the Complementary MOS (CMOS) structure, when a stress is applied to the n-channel MOSFET to stretch the whole channel as well as applied to the p-channel MOSFET to compress the whole channel in the source-drain direction, each channel mobility of carriers can be improved.
However, the speeding up of the MOSFET is further requested recently. Therefore, it becomes difficult to apply a sufficient strain to a channel by individually applying the above-described techniques.
In addition, it is needed to simply and effectively apply a stress to a channel in order to suppress process costs.
In terms of costs, the above-described technique for covering the MOSFET with the CESL film is preferred. However, when a intrinsic stress of a film is excessively increased in order to apply a higher stress to a channel, a warpage occurs in a wafer itself. As a result, it becomes difficult to perform a lithography process of forming a pattern. Accordingly, there are limitations in improving the intrinsic stress of a film.
Therefore, plural techniques must be heretofore used at the same time to improve the stress applied to a channel. However, this case has a problem that the process costs more increase.